Field effect devices, such as field effect transistors, are fundamental components in modem electronics. They are basic components in most digital and many analog circuits, including circuits for data processing and telecommunications. Indeed it has been surmised that field effect transistors are among the most numerous of human-made objects.
Field effect devices typically comprise a controllable-conductivity path, called a channel, disposed between a source and a drain. A gate electrode is formed on a thin dielectric film overlying the channel. For example, the source and the drain can be n-type regions of silicon, and the channel can be a p-type region connecting them. The gate electrode can be a conductively doped polysilicon layer formed on a thin layer of silicon oxide dielectric overlying the channel.
If no voltage is applied to the gate, current cannot flow from the source to the channel or from the channel to the drain. However if a sufficient positive voltage is applied to the gate, electrons are induced into the channel region, thereby creating a continuous n-type conductive path between the source and the drain.
Capacitors are also important components of integrated circuits. A typical capacitor comprises first and second conductive layers separated by a thin dielectric film.
The reliable operation of integrated circuits is critically dependent on the reliability of the increasingly thin dielectric layers used in circuit devices. As transistors have become smaller and more densely packed, the dielectrics have become thinner. Capacitor and gate dielectrics are often less than 80 angstroms in thickness. With the arrival of ULSI technology, gate dielectrics are approaching 50 angstroms or less. For integrated circuits to work, these thin layers in each of thousands of different transistors must provide sufficient capacitance to drive the device, protect the channel from migration of impurities and avoid production of charge traps at their interfaces. These demanding requirements may soon exceed the capacities of conventional silicon oxide layers. Silicon oxide layers less than 2 nm will have prohibitively large leakage currents.
Efforts to replace silicon oxide as the gate dielectric have thus far proved less than satisfactory. Because of its relatively low dielectric constant (.apprxeq.3.9), the largest capacitance obtainable with a thin layer of silicon oxide is about 25 fF/.mu.m.sup.2. This limits the scaling of transistors to smaller sizes because the capacitance will not be sufficient to drive the device. Higher dielectric constant tantalum oxide has been tried, but results are poor due to a high density of charge traps at the dielectric/silicon interface. Composite layers of SiO.sub.2 /Ta.sub.2 O.sub.5 and SiO.sub.2 /Ta.sub.2 O.sub.5 /SiO.sub.2 were tried, but the necessary resulting thicknesses limit the capacitance which can be obtained. Efforts have also been made to prevent charge traps by depositing a thin layer of silicon nitride between the silicon and the tantalum oxide. But the nitride layer also reduces the capacitance and thus limits scaling of the device. See U.S. Pat. No. 5,468,687 issued to D. Carl et al on Nov. 21, 1995 and Y. Momiyama et al, "Ultra-Thin Ta.sub.2 O.sub.5 /SiO.sub.2 Gate Insulator with TiN Gate", 1997 Symposium on VLSI Technology, Digest of Technical Papers, pp. 135-136. Accordingly, there is a need for an improved method for making devices having thin layers of high dielectric constant.